Under the tendency of development of highly integrated semiconductors, after multi-wafer stacking, a manner of lead bonding is generally adopted to realize interconnection among multiple wafers. Specifically, multiple wafers are stacked along a vertical direction on a special silicon substrate. Each wafer has multiple bonding pads used for interconnection, a plurality of sharing bonding pads are arranged on the silicon substrate. One end of each of leads is bonded to a corresponding one of the bonding pads of the wafer in a pressure welding manner, and the other end of each of the leads are bonded to a corresponding one of the sharing bonding pads of the silicon substrate in an integrated pressure welding manner, so as to realize interconnection among the multiple wafers.
But the inventor finds that some problems exist in the traditional multi-wafer lead interconnection manner. Firstly, there are certain restrictions on the thickness of the wafers with the development of multi-wafer stacking towards high density. As a pressure welding lead space needs to be reserved among multiple wafers adopting lead bonding, the silicon substrate itself has a certain thickness, and the overall thickness after multi-wafer stacking is relatively great to a certain extent. In addition, gold wires are generally adopted as the leads, and therefore, the cost is relatively high. Moreover, the leads result in a relatively long interconnection line, which reduces the signal transmission speed and increases the power loss. Furthermore the silicon substrate cannot be adapted to the requirement on more and more sharing bonding pads for high-density development of the multi-wafer stacking.